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Avago AFBR-785BPZ Twelve-Channel Receiver

AFBR-785BPZ

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Specifications

  • 产品型号: AFBR-785BPZ
  • 兼容品牌: 安化高Avago
  • 封装类型: Avago AFBR-785BPZ Twelve-Channel Receiver
  • 传输速率: Avago AFBR-785BPZ Twelve-Channel Receiver
  • 传输距离: Avago AFBR-785BPZ Twelve-Channel Receiver
  • 发射波长: 850nm
  • 吸收波长: 850nm
  • 事情温度: 商业级0℃～+70℃/工业级-40℃～+85℃ 可选
  • 数字诊断: 带DDM/不带DDM 可选
  • 吸收迅速度: Avago AFBR-785BPZ Twelve-Channel Receiver
  • 吸收迅速度: Avago AFBR-785BPZ Twelve-Channel Receiver

Description

AFBR-785BPZ Twelve-Channel Transmitter and Receiver Pluggable, Parallel-Fiber-Optics Modules

Description

AFBR-785BPZ Twelve-Channel Transmitter and Receiver Pluggable, Parallel-Fiber-Optics ModulesThe AFBR-785BPZ Twelve-Channel, Pluggable, Parallel- Fiber-Optics Transmitter and AFBR-785BPZ Twelve- Channel, Pluggable, Parallel-Fiber-Optics Receiver  are  high performance fiber optics modules for short-range parallel multi-lane data communication and interconnect applications. The modules operate at 5.0Gbps per channel over multimode fiber systems using a nominal wave- length of 850 nm. Aggregate bandwidth per transmitter- receiver link is 60G. The electrical interface uses a 10x10 MEG-Array? low-profile mezzanine connector. The optical interface uses a MTP? (MPO) 1x12 ribbon cableconnector. The thermal interface can be a factory installed heatsink for air-cooled systems or thermal seating plane for user flexibility. The modules incorporate high performance, highly reliable, short wavelength optical devices coupled with proven circuit technology to provide long life and consistentservice.

Applications

  • High Performance and High Productivity computer interconnects
  • InfiniBand12XDDRSXinterconnects
  • Datacomswitchandrouterbackplaneconnections
  • Telecomswitchandrouterbackplaneconnections
  • Dense4GbpsFibreChannelcompatiblearchitectures
  • Reach extensions for various protocols including PCI Express, HyperTransport and Serial RapidIO

Features

  • HighChannelCapacity:60Gbpspermodule
  • High port density: 19 mm lateral port pitch; < 0.51 mm/ Gbps for Tx–Rxpair
  • LowpowerconsumptionperGbps:<53mW/Gb/sfor Tx–Rxpair
  • Based on industry-standard, pluggable, SNAP12 form factor with upgraded pinout for improved signal integrity and keyed to prevent mis-plugging with first generation  SNAP12devices
  • Backed by PPOD MSA to enable multiple sources of supply
  • Twelveindependentchannelspermodule
  • Separate transmitter and receivermodules
  • 850 nm VCSEL array in transmitter; PIN array inreceiver
  • Operatesupto5.0Gbpswith8b/10bcompatiblecoded data
  • Links up to 150 m at 5.0 Gbps with 2000 MHz?km 50um MMF
  • Two power supplies, 2.5 V and 3.3 V, for low power consumption
  • Dedicated signals for module address, module reset and hostinterrupt.
  • TwoWireSerial(TWS)interfacewithmaskableinterrupt for  expanded  functionalityincluding:
  • Individual channel functions: disable, squelch disable,lanepolarityinversion,margin
  • Programmable equalization integrated with DC blockingcapsattransmitterdatainput
  • Programmable receiver output swing and de- emphasislevel
  • A/D readback: module temperature and supply voltages, per channel laser current and laser power, or receivedpower
  • Status: per channel Tx fault, electrical (transmitter) or optical (receiver) LOS, and alarmflags
  • 0 to 80 °C case temperature operating range

Transmitter Part Numbers

  • With fin heat sink / no EMI nose clip AFBR-775BZ
  • With fin heat sink / EMI nose clip AFBR-77BEZ
  • With pin heat sink / no EMI nose clip AFBR-775BPZ
  • With pin heat sink / EMI nose clip AFBR-775BEPZ
  • With no heat sink / no EMI nose clip AFBR-775BHZ
  • With no heat sink / with EMI nose clip AFBR-775BEHZ

Receiver Part Numbers

  • With fin heat sink / no EMI nose clip AFBR-785BZ
  • With fin heat sink / EMI nose clip AFBR-785BEZ
  • With pin heat sink / no EMI nose clip AFBR-785BPZ
  • With pin heat sink / EMI nose clip AFBR-785BEPZ
  • With no heat sink / no EMI nose clip AFBR-785BHZ
  • With no heat sink / with EMI nose clip AFBR-785BEHZ

Transmitter Module

The optical transmitter module (see Figure 1) incorpo- rates a 12-channel VCSEL (Vertical Cavity Surface Emitting Laser) array, a 12-channel input buffer and laser driver, di- agnostic monitors, control and bias blocks. The transmit- ter is designed for IEC-60825 and CDRH eye safety com- pliance; Class 1M out of the module. The Tx Input Buffer provides CML  compatible  differential  inputs  (presenting a nominal differential input impedance of 100 Ohms and   a nominal common mode  impedance  to  signal  ground  of 25 Ohms) for the high speed electrical interface that can operate over a wide common mode range without requiring DC blocking capacitors. For module control and interrogation, the control interface (LVTTL compatible) incorporates a Two Wire Serial (TWS) interface of clock and data signals and dedicated signals for host interrupt, module address setting and module reset. Diagnostic monitors for VCSEL bias, light output (LOP), temperature, both supply voltages and elapsed operating time are implemented and results are available through the TWS interface.

Over the TWS interface, the user can, for individual channels, control (flip) polarity of the differential inputs, de-activate channels, place channels into margin mode, disable the squelch function and program input equaliza- tion levels to reduce the effect of long PCB traces. A reset for the control registers is available. Serial ID information and alarm thresholds are provided. To reduce the need for polling, the TWS interface is augmented with an interrupt signal for the host.

Alarm thresholds are established for the monitored attri- butes. Flags are set and interrupts generated when the attributes are outside the thresholds. Flags are also set and interrupts generated for loss of input signal (LOS) and transmitter fault conditions. All flags are latched and will remain set even if the condition initiating the latch clears and operation resumes. All interrupts can be masked and flags are reset by reading the appropriate flag register.  The optical output will squelch for loss of input signal unless squelch is disabled. Fault detection or channel deactivation  through  the  TWS  interface  will  disablethe

channel. Status, alarm and fault information are available via the TWS interface. The interrupt signal (selectable via the TWS interface as a pulse or static level) is provided to inform hosts of an assertion of an alarm, LOS and/or Tx fault.

 

Receiver Module

The optical receiver module (see Figure 2) incorporates      a 12-channel PIN photodiode array, a 12-channel pre- amplifier and output buffer, diagnostic monitors, control and bias blocks. The Rx Output Buffer provides CML com- patible differential outputs for the high speed electrical interface presenting nominal single-ended output im- pedances of 50 Ohms to AC ground and 100 Ohms dif- ferentially that should be differentially terminated with 100 Ohms. DC blocking capacitors may be required. For module control and interrogation, the control interface (LVTTL compatible) incorporates a Two Wire Serial (TWS) interface of clock and data signals and dedicated signals for host interrupt, module address setting and module reset. Diagnostic monitors for optical input power, tem- perature, both supply voltages and elapsed operating  time are implemented and results are available through the TWSinterface.

Over the TWS interface, the user can, for individual channels, control (flip) polarity of the differential outputs, de-activate channels, disable the squelch function, program  output  signal  amplitude  and   de-emphasis   and change receiver bandwidth. A reset for the control registers is available. Serial ID information and alarm thresholds are provided. To reduce the need for polling, the TWS interface is augmented with an interrupt signal for thehost.

Alarm thresholds are established for the monitored attri- butes. Flags are set and interrupts generated when the attributes are outside the thresholds. Flags are also set and interrupts generated for loss of optical input signal (LOS).   All flags are latched and will remain set even if    the  condition  initiating  the  latch  clears  and   operation

resumes. All interrupts can be masked and flags are reset upon reading the appropriate flag register.  The  elec-  trical output will squelch for loss of input signal (unless squelch is disabled) and channel de-activation through TWS interface. Status and alarm information are available via the TWS interface. The interrupt signal (selectable via the TWS interface as a pulse or static level) is provided to inform hosts of an assertion of an alarm and/orLOS.

 

Important Notice

Performance figures, data and any illustrative material provided in this data sheet are typical and must be specifically confirmed in writing by F-tone Networksbefore they become applicable to any particular order or contract. In accordance with the F-tone Networks policy of continuous improvement specifications may change without notice.

The publication of information in this data sheet does not imply freedom from patent or other protective rights of F-tone Networks or others. Further details are available from any F-tone Networks sales representative.

 

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